Hash engines

SHA-256 performance lane

One CompressionLane contains a 64-stage round pipeline. Each accepted token carries:

• eight working words;
• a sixteen-word rolling message-schedule window;
• the original chaining value for feed-forward;
• a 32-bit opaque task tag; and
• a valid bit.

The original chaining value is aligned in synchronous memory while the round state moves through the pipeline. A valid result appears after exactly 64 cycles. Reset clears validity and due ownership; wide datapath registers are intentionally resetless where validity makes their contents unobservable.

ThreeLaneCompressionFarm is a standalone generation and equivalence target: it elaborates three independent lane instances from one repeated RHDL prototype and can exercise all three in parallel. It is not instantiated by the production signer.

The production signer instead has three autonomous four-context clusters. Each cluster owns one complete compression lane shared by its four contexts, for three independent lane instances in the authored hierarchy. A single textual lane-module definition does not establish mapped hardware. Only synthesis can report the physical resource implementation.

Legacy Keccak compatibility engine

The legacy profile uses Keccak-256 with a 136-byte rate and 0x01 domain byte. The area-oriented IterativeKeccak stores one 1,600-bit state and applies one of 24 rounds per cycle. Complete combinational round and permutation exports exist as correctness or lowering artifacts, not as the selected high-throughput architecture.

SHA3-256 uses a different domain encoding and produces unrelated digests. A refactor must never replace legacy Keccak with SHA3 under the same profile name.

DSP interpretation

Source annotations and arithmetic structure may encourage DSP inference, but a DSP count is a synthesis result. Generated Verilog simulation cannot establish whether Vivado maps additions, schedule arithmetic, or other operations into DSP48E2 blocks.