pub fn generate_round_verilog() -> Result<String, RHDLError>Expand description
Generate a standalone combinational one-round Verilog module.
The generated keccak_round_ooc top accepts and produces a 1,600-bit state.
Round zero’s Iota constant is bound at compile time, so the isolated top has
no round-constant mux. RHDL’s pure synchronous-function wrapper also emits
an unused two-bit clock/reset port; the datapath itself is combinational.
It contains no handwritten cryptographic Verilog. This API is intended for
the downstream RTL exporter and isolated synthesis experiments.
§Errors
Returns an RHDL compilation or Verilog-lowering error.