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compression_lane_checked_verilog

Function compression_lane_checked_verilog 

Source
pub fn compression_lane_checked_verilog<const ROUNDS: usize, const ADDRESS_BITS: usize>() -> Result<String, RHDLError>
where W<ROUNDS>: BitWidth, W<ADDRESS_BITS>: BitWidth,
Expand description

Emits and Icarus-checks a power-of-two lane specialization.

This is intended for small specializations because the pinned RHDL release emits the complete round array as one monolithic function; Icarus Verilog 13 cannot lex the full 64-stage form.

ยงErrors

Returns an error if the specialization is invalid, RHDL lowering fails, or Icarus rejects the generated module hierarchy.