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try_full_three_lane_farm_generation_only_unchecked_verilog

Function try_full_three_lane_farm_generation_only_unchecked_verilog 

Source
pub fn try_full_three_lane_farm_generation_only_unchecked_verilog() -> Result<String, RHDLError>
Expand description

Renders the complete three-lane farm while bypassing its final Icarus check.

The word unchecked in this function’s name is an evidence warning. The pinned RHDL core is patched locally so nested composition consumes raw child descriptors rather than re-running Icarus for every hierarchy level. Icarus Verilog 13 still overflows its scanner on the monolithic 64-stage functions, so callers must pass the result through a capable parser such as Verilator or Vivado. The returned text alone is only generated-Verilog evidence: it has not been parsed, simulated, proven equivalent, synthesized, placed, routed, timed, or executed on hardware.

§Errors

Returns an error if RHDL cannot construct or render the full descriptor.