Canonical evidence · schema v1

Every claim keeps its producing tier.

This matrix is generated from manifest.json and checked by the strict in-repository validator. The published schema is the matching contract for external consumers. Pending rows are explicit nonclaims, not inferred results.

Evidence matrix

RecordStatusTierProfileTopology
Pinned HashSigsRS legacy WOTS vectors passed Rust/RHDL source simulation LEGACY_KECCAK Software reference oracle; five upstream WOTS vectors
Production signer source simulation passed Rust/RHDL source simulation HASHSIGS_SHA256_GENERIC_V1 Three clusters × four contexts with three complete SHA-256 lanes
Three-cluster SHA-256 verifier source simulation passed Rust/RHDL source simulation HASHSIGS_SHA256_GENERIC_V1 Three clusters × four contexts with three complete SHA-256 lanes
Replicated three-lane SHA-256 arithmetic passed Generated RTL simulation HASHSIGS_SHA256_GENERIC_V1 Three independent 64-stage compression lanes
Production signer generated-Verilog equivalence passed Generated RTL simulation HASHSIGS_SHA256_GENERIC_V1 Three clusters × four contexts; one linked lane definition elaborated three times
Production signer sustained generated-RTL throughput passed Generated RTL simulation HASHSIGS_SHA256_GENERIC_V1 Three clusters × four contexts; continuous admission and always-ready output
Production signer U280 synthesis at 250 MHz pending U280 synthesis HASHSIGS_SHA256_GENERIC_V1 Raw production signer top; three clusters × four contexts
Production signer U280 synthesis at 300 MHz pending U280 synthesis HASHSIGS_SHA256_GENERIC_V1 Raw production signer top; three clusters × four contexts
Production signer U280 route at 250 MHz pending U280 placement and route HASHSIGS_SHA256_GENERIC_V1 Raw production signer top; three clusters × four contexts
Production signer U280 route at 300 MHz pending U280 placement and route HASHSIGS_SHA256_GENERIC_V1 Raw production signer top; three clusters × four contexts
Production signer U280 card execution pending Card execution HASHSIGS_SHA256_GENERIC_V1 Production signer plus a separately validated U280 shell

Evidence ladder

Tier 0

Model

Software-oracle, dependency, or arithmetic-model behavior for the stated inputs.

does not prove RHDL behavior; generated RTL; synthesis; timing; route; hardware

Tier 1

Rust/RHDL source simulation

Behavior of the exact Rust/RHDL source in the executed finite trace.

does not prove generated RTL equivalence; mapped resources; timing; route; hardware

Tier 2

Generated RTL simulation

Lowering equivalence for the exact generated RTL and executed trace.

does not prove formal proof; four-state proof; synthesis; timing; route; hardware

Tier 3

U280 synthesis

Mapped resource and synthesis timing estimates for the exact top, part, source, and constraint.

does not prove complete placement; complete route; shell timing; card throughput

Tier 4

U280 placement and route

Resource and timing reports for a completely routed exact design.

does not prove card execution; untested shell behavior; unmeasured workloads

Tier 5

Card execution

Validated runtime behavior and throughput for the exact programmed artifact and workload.

does not prove other source revisions; other clocks; other shells; untested workloads