integration · 2026-07-15

Production signer U280 synthesis at 250 MHz

This row reserves the synthesis gate. It carries no U280 result until exact staged provenance and reports are recorded.

pending HASHSIGS_SHA256_GENERIC_V1

Identity and boundary

Evidence tier: U280 synthesis
Topology: Raw production signer top; three clusters × four contexts
Cryptographic subject/source commit: dbd18593527673be2a93d7067ee03667892c582a
Cryptographic source dirty: no
Producing narrative: Read the privacy-sanitized source record
fpga/u280/README.md

Measurements

No measurement is recorded at this pending boundary.

Supported claims

This pending gate supports no claims.

Explicit nonclaims

synthesis pass
mapped resources
250 MHz timing
placement, route, shell, or hardware throughput

Tools

No producing tool is recorded at this pending boundary.

Artifacts

Artifact	Published bytes	SHA-256
candidate linked signer bundle	Digest only	`41fe7ba31ec811b6a69ebcb9d2e76af512b0b49af99b7c83389d5cf97b978e68`

Next gate

Create a fresh schema-v2 baseline stage (the preserved 6801a66 stage is unlaunchable), then run isolated checksum-bound synthesis for xcu280-fsvh2892-2L-e at a 4.000 ns constraint and archive the applied/observed constraint reports with all other reports.