u280_shell_rhdl/
axi.rs

1//! Exact packed AXI4-Lite and 512-bit AXI4 channel types.
2
3use rhdl::prelude::*;
4
5/// Successful AXI response.
6pub const AXI_RESP_OKAY: b2 = b2(0);
7/// Exclusive success is deliberately rejected by this kernel.
8pub const AXI_RESP_EXOKAY: b2 = b2(1);
9/// Mapped access with invalid permissions or state.
10pub const AXI_RESP_SLVERR: b2 = b2(2);
11/// Unmapped or misaligned control access.
12pub const AXI_RESP_DECERR: b2 = b2(3);
13/// One 64-byte transfer.
14pub const AXI_SIZE_64_BYTES: b3 = b3(6);
15/// Fixed burst encoding.
16pub const AXI_BURST_FIXED: b2 = b2(0);
17/// Incrementing burst encoding.
18pub const AXI_BURST_INCR: b2 = b2(1);
19/// Normal nonexclusive access.
20pub const AXI_LOCK_NORMAL: b2 = b2(0);
21/// Normal, non-buffered cache attributes used by the U280 shell.
22pub const AXI_CACHE_NORMAL: b4 = b4(0b0011);
23
24/// Host-to-kernel AXI4-Lite signals.
25#[allow(clippy::struct_excessive_bools)] // Preserve the fixed packed AXI channel ABI and port layout.
26#[derive(Clone, Copy, Debug, Default, Digital, Eq, PartialEq)]
27pub struct AxiLiteHostToKernel {
28    /// Write-address validity.
29    pub awvalid: bool,
30    /// Eight-bit byte address.
31    pub awaddr: b8,
32    /// Write-data validity.
33    pub wvalid: bool,
34    /// Write data.
35    pub wdata: b32,
36    /// Per-byte write enables.
37    pub wstrb: b4,
38    /// Host acceptance of the write response.
39    pub bready: bool,
40    /// Read-address validity.
41    pub arvalid: bool,
42    /// Eight-bit byte address.
43    pub araddr: b8,
44    /// Host acceptance of the read response.
45    pub rready: bool,
46}
47
48/// Kernel-to-host AXI4-Lite signals.
49#[allow(clippy::struct_excessive_bools)] // Preserve the fixed packed AXI channel ABI and port layout.
50#[derive(Clone, Copy, Debug, Default, Digital, Eq, PartialEq)]
51pub struct AxiLiteKernelToHost {
52    /// Write-address acceptance.
53    pub awready: bool,
54    /// Write-data acceptance.
55    pub wready: bool,
56    /// A write response is available.
57    pub bvalid: bool,
58    /// Write response code.
59    pub bresp: b2,
60    /// Read-address acceptance.
61    pub arready: bool,
62    /// A read response is available.
63    pub rvalid: bool,
64    /// Read data.
65    pub rdata: b32,
66    /// Read response code.
67    pub rresp: b2,
68}
69
70/// HBM0-to-kernel signals for the read-only input master.
71#[derive(Clone, Copy, Debug, Digital, Eq, PartialEq)]
72pub struct Axi512ReadMemoryToKernel {
73    /// Memory acceptance of the read address.
74    pub arready: bool,
75    /// Read data is available.
76    pub rvalid: bool,
77    /// One 512-bit line, byte lane zero at the lowest packed bits.
78    pub rdata: [b8; 64],
79    /// Response ID.
80    pub rid: b1,
81    /// Response status.
82    pub rresp: b2,
83    /// Final response beat.
84    pub rlast: bool,
85}
86
87impl Default for Axi512ReadMemoryToKernel {
88    fn default() -> Self {
89        Self {
90            arready: false,
91            rvalid: false,
92            rdata: [b8(0); 64],
93            rid: b1(0),
94            rresp: AXI_RESP_OKAY,
95            rlast: false,
96        }
97    }
98}
99
100/// Kernel-to-HBM0 signals for the read-only input master.
101#[derive(Clone, Copy, Debug, Default, Digital, Eq, PartialEq)]
102pub struct Axi512ReadKernelToMemory {
103    /// Read address is valid and stable until accepted.
104    pub arvalid: bool,
105    /// Byte address.
106    pub araddr: b64,
107    /// Single supported transaction ID, always zero.
108    pub arid: b1,
109    /// Number of beats minus one, always zero for input jobs.
110    pub arlen: b8,
111    /// Log2 bytes per beat, always six.
112    pub arsize: b3,
113    /// Incrementing burst.
114    pub arburst: b2,
115    /// Normal access.
116    pub arlock: b2,
117    /// Cache attributes.
118    pub arcache: b4,
119    /// Protection attributes.
120    pub arprot: b3,
121    /// Quality of service.
122    pub arqos: b4,
123    /// Region tag.
124    pub arregion: b4,
125    /// Kernel acceptance of a read response.
126    pub rready: bool,
127}
128
129/// HBM1-to-kernel signals for the write-only output master.
130#[derive(Clone, Copy, Debug, Default, Digital, Eq, PartialEq)]
131pub struct Axi512WriteMemoryToKernel {
132    /// Memory acceptance of the write address.
133    pub awready: bool,
134    /// Memory acceptance of one data beat.
135    pub wready: bool,
136    /// A write response is available.
137    pub bvalid: bool,
138    /// Response ID.
139    pub bid: b1,
140    /// Response status.
141    pub bresp: b2,
142}
143
144/// Kernel-to-HBM1 signals for the write-only output master.
145#[allow(clippy::struct_excessive_bools)] // Preserve the fixed packed AXI channel ABI and port layout.
146#[derive(Clone, Copy, Debug, Digital, Eq, PartialEq)]
147pub struct Axi512WriteKernelToMemory {
148    /// Write address is valid and stable until accepted.
149    pub awvalid: bool,
150    /// Byte address.
151    pub awaddr: b64,
152    /// Single supported transaction ID, always zero.
153    pub awid: b1,
154    /// Number of beats minus one.
155    pub awlen: b8,
156    /// Log2 bytes per beat, always six.
157    pub awsize: b3,
158    /// Incrementing burst.
159    pub awburst: b2,
160    /// Normal access.
161    pub awlock: b2,
162    /// Cache attributes.
163    pub awcache: b4,
164    /// Protection attributes.
165    pub awprot: b3,
166    /// Quality of service.
167    pub awqos: b4,
168    /// Region tag.
169    pub awregion: b4,
170    /// Write data is valid and stable until accepted.
171    pub wvalid: bool,
172    /// One 512-bit line, byte lane zero at the lowest packed bits.
173    pub wdata: [b8; 64],
174    /// Per-byte write enables.
175    pub wstrb: b64,
176    /// Final data beat.
177    pub wlast: bool,
178    /// Kernel acceptance of a write response.
179    pub bready: bool,
180}
181
182impl Default for Axi512WriteKernelToMemory {
183    fn default() -> Self {
184        Self {
185            awvalid: false,
186            awaddr: b64(0),
187            awid: b1(0),
188            awlen: b8(0),
189            awsize: AXI_SIZE_64_BYTES,
190            awburst: AXI_BURST_INCR,
191            awlock: AXI_LOCK_NORMAL,
192            awcache: AXI_CACHE_NORMAL,
193            awprot: b3(0),
194            awqos: b4(0),
195            awregion: b4(0),
196            wvalid: false,
197            wdata: [b8(0); 64],
198            wstrb: b64(0),
199            wlast: false,
200            bready: false,
201        }
202    }
203}
204
205/// Canonical idle input-read master signals.
206#[kernel]
207pub fn idle_read_master_kernel() -> Axi512ReadKernelToMemory {
208    Axi512ReadKernelToMemory {
209        arvalid: false,
210        araddr: b64(0),
211        arid: b1(0),
212        arlen: b8(0),
213        arsize: AXI_SIZE_64_BYTES,
214        arburst: AXI_BURST_INCR,
215        arlock: AXI_LOCK_NORMAL,
216        arcache: AXI_CACHE_NORMAL,
217        arprot: b3(0),
218        arqos: b4(0),
219        arregion: b4(0),
220        rready: false,
221    }
222}
u280_shell_rhdl/axi.rs

u280_shell_rhdl/
axi.rs
